Synaptics

Senior Digital Design Engineer

Job Locations US-CA-San Jose
ID
2021-2619
Category
R&D
Type
Employee

Overview

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

 

Responsibilities

Synaptics Mobile silicon design team is continuously developing new design and IPs for various projects, such as touch controller, display drive controller, TDDI and LTDI system and is seeking a Senior Design Engineer. The candidate will be responsible for micro-architecture and logic design. The candidate will also be closely working with verification team on running functional simulation in block level, top level and chip level simulation environments. Furthermore, the candidate will also work with test team on various silicon debug activities.

• Create module specification & block level microarchitecture.
• Model and analyze performance, area, and system cost tradeoffs for different micro-architectures. Present compelling arguments for an optimal solution based on analyses.
• Implement module and chip-level designs in Verilog hardware design language.
• Work with the verification team to confirm the correctness of design and help to debug simulations.
• Work with physical design engineers to plan block layout, synthesize designs, formally check synthesis results, and achieve both block and full-chip timing closure.
• Participate in silicon debug and analysis if needed.
• Schedule tasks and goals to complete designs on time that meet all specifications

 

Qualifications

• BS in Electrical Engineering with 5 or more years of industry experience; or MS in Electrical Engineering with 3 or more years of industry experience is required.
• Hands-on experience in synthesis and timing analysis will be desirable
• Experience in using IC design tools such as Synopsys VCS or Cadence IRUN is required. Experience in Design Compiler and Primetime will be desirable but not required.
• Working knowledge of programming and scripting languages such as C, Perl or TCL will be helpful but not required.
• A good understanding of testability and design-for-test (DFT), ATPG, BIST is a big plus.
• Firmware development (using C or Assembly) experience is highly desired but not required.

 

If you are hired, we will require you to prove that you have received the COVID-19 vaccine or have a valid religious or medical reason not to be vaccinated. 

 

#LI-TT1

 

Options

Sorry the Share function is not working properly at this moment. Please refresh the page and try again later.
Share on your newsfeed