Synaptics

Senior Staff Design Verification Engineer

Job Locations IL-Herzliya
ID
2022-2804
Category
R&D
Type
Employee

Overview

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Responsibilities

We seek to consistently deliver next-generation solutions in audio, LP - AI, and Wireless smart sensors. We are looking for a talented and experienced Design Verification (DV) Engineer to build an environment that will provide the confidence that the design will meet datasheet specifications.

DV leading engineer is responsible for leading the verification team, Defining and building verification methodology, and testing concepts. Mentoring junior engineers and monitoring the DV development.

  • Be a part of the verification methodology development for all levels within the IP/subsystem.
  • Define and execute detailed verification plan from spec/standard working with designers and system engineer (architects) teams and build according to the required verification environment.
  • Mentoring junior engineers.
  • Use System Verilog language and UVM to develop an extendable environment incorporating C reference models.
  • Find and debug failure within the (design and verification) and collaborate with the architect, design, and DV engineers to identify the failure’s root cause.
  • Collaborate with other verification team members in the organization across multiple sites.

Qualifications

  • B.Sc in Computer or Electrical Engineering.
  • Have a minimum of 5 years of experience as a Verification engineer.
  • Have deep knowledge of SV language and UVM methodology and usage of C models DPI’s.
  • hold wide and deep experience in block-level verification – from scratch environment buildup, verification plan buildup, coverage, analysis, and debug, preparing it for higher-level integration.
  • Verification experience on WIFI PHY, algorithmic blocks, mixed-signal verification is an enormous plus.

Humanly, with an analytical mind that enjoys working in a team.



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