Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Job Responsibilities

The Edge SoC Silicon R&D team is looking for a hands-on, team oriented engineer with SoC/ASIC implementation expertise. In this individual contributor role, candidate will have complete ownership of SoC/ASIC STA (subsystem or full chip level) from RTL to timing closure. Candidate should have hands-on knowledge of Synthesis, Formal Verification, Static Timing Analysis, Low Power methologies and DFT at Physical partition or full chip level of SoC/ASIC. Candidate should have strong ability to learn and explore new technologies. Candidate is desired to have expertise in SoC/ASIC CAD tool (SoC/ASIC implementation) flow development and ability to demonstrate good analysis and problem-solving skills. Candidate is desired to have an extraordinarily creative and motivated  approach towards complex design problems. Candidate must be highly organized, able to prioritize, and juggle multiple work streams towards tight deadlines.

• 5+years of SoC/ASIC implementation cycle with good working understanding/experience/knowledge of following is must:
  • Study of Functional Specification/Requirement documents, Standard documents to extract key information required for ASIC/SoC implementation flows
  • SoC/ASIC Physical-partition/full-chip floorplan experience
  • Clock, Reset Structures/Schemes
  • Synthesis/STA Constraint modelling/validation
  • Clock-Structure analysis, Reset-Structure analysis
  • Synthesis/STA Constraint modelling/validation
  • Logic Synthesis (using Design-Compiler or equivalent industry tools)
  • Formal Verification (using Formality, Conformal or equivalent industry tools)
  • CDC (using Spyglass or equivalent industry tools)
  • Static Timing Analysis (using Primetime or Encounter Timing System)
  • Power Analysis (Primepower or equivalent industry tools)
  • Interaction/co-ordination with different cross-functional (digital-design/analog-design/physical-design/verification) teams across different world geographies
  • ASIC tool flow environment setup: Spyglass-lint/CDC, Design Compiler(T), Formality, PrimeTime, PrimePower
  • DFT Techniques/Structures
  • Scripting: Perl, Tcl, Shell languages

• Following skills are must:
  • Hands on synthesis, timing closure experience of minimum 3 tape-out cycles at physical-partition/block/tile or chip level, delivering best Power Performance Area for block/tile with critical high-speed path timing closure
  • Strong Analytical, Problem solving, Debugging skills
  • Excellent Oral/Written Communication and Technical Documentation Skills
  • Knowledge of revision control tools such as SOS, Git, synchronicity etc.

• Following additional skills a plus:
  • Knowledge and exposure to complete RTL to GDS release flow is desired
  • Hands on experience with MBIST, Scan insertion, ATPG, BIST, JTAG, physical design tools and flow.
  • Hands on experience with Low power design methodology & techniques like UPF, DVFM, Multi-voltage etc.

• BE/BTech/ME/MTech in Electrical/Electronics/VLSI Design/Communications or a related technical discipline