Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.
We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.
Role and Responsibilities:
Deliver Complex Block level or Chip (SOC/ASIC) level place and route from Netlist to GDS for different Synaptics products.
Perform physical design in digital top or analog top design approach based on project needs.
Perform full chip feasibility and die size estimation by addressing design challenges to meet Power, Performance and Area requirements.
He/She should be able to setup and do Floor planning, PG planning, Partitioning, Placement, Scan-Chain re-ordering, Clock tree synthesis, timing optimization, SI aware routing, Timing analysis/closure and ECO tasks(Functional and timing ECOs), SI closure, Physical verification(DRC/LVS/ANT) closure, Logical Equivalence Check and EM/IR closure.
Responsible for design, planning, scheduling and execution of Physical design function of the project.
Provide technical guidance, mentoring to less experienced physical design engineers.
Ability to interface with different teams and prioritize work based on project needs.
Builds strong business relationships with cross-functional teams for smoother execution of projects.
Work closely with Synaptics Global Digital Design, Analog Design, Layout Design and CAD engineering teams.
Experience with Prime Time and Prime Time SI is a plus.
Experience with IR/EM Redhawk tool for dynamic analysis.
Location: Bangalore, India
Bachelor’s or Master’s in Electrical Engineering or ECE or EEE.
5+ years relevant experience in Physical Design Implementation.
Experience in CMOS, FDSOI and FinFET technologies and nodes ranging from 180nm to 12nm.
Expertise with SOC and ASIC design flows, procedures and deliverables.
Expert in physical implementation of high-speed designs closure.
Experience in hierarchical design, budgeting, multi voltage domains and multiple clock domains.
Strong knowledge of low power design techniques and deep sub-micron issues.
Experience with Synopsys Reference Methodologies flows for Block and SOC level implementation.
Hands-on experience with EDA tools - Synopsys (ICC, ICC2, DC, PT, STARRC), Mentor (Calibre) and Ansys (Redhawk).
Expert in scripting languages (TCL, PERL) to automate the flow.
Strong analytical, debug and problem-solving skills in resolving design challenges, timing issues and physical verification issues.
Flexible to work in a cross functional and multi-site team environment, spanning different time zones.
Must have good verbal and written communication skills.
Analyze timing within PD environment and using STA tools, to achieve timing closure by generating and applying ECO to layout is a plus.