Synaptics

Sr Staff Engineer - WLAN PHY Design

Job Locations IN-Bengaluru
ID
2022-3050
Category
R&D
Type
Employee

Overview

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

 

Background

Synaptics Inc is building a world-class franchise around WiFi/BT products targeted towards IoT applications. As part of this push to be the go-to vendor for connectivity solutions for IoT, a new silicon development team is being built in Bangalore. The team will have complete ownership of connectivity products right from architecture, specification development, design, design verification, integration, emulation, tapeout and production. The team is viewed as a “start-up” within Synaptics umbrella and is looking for highly motivated, talented members to create next generation products.

 

Job Scope

  • Location: Bangalore, India
  • To drive the SOC in the Wifi 6E/7 + BT domain from concept to volume production in timely manner.
  • Provide technical leadership and expertise in the SOC as well as Wifi domain.
  • Responsible for overall chip schedule and coordinating with multiple teams on specifications, deliverables, handoff, verification and timing closure.
  • Work closely with RF/Analog teams for productizing WLAN/BT combo chips for home IOT and automotive markets.
  • Leadership role in architecting area and power efficient low latency designs with scalabilities and flexibilities
  • Drive innovations in the low power design, performance enhancements etc.

Responsibilities

Job Responsibilities

  • Define SOC architecture from the standards and/or requirement documents
  • Define SOC PPA (power, performance and area) parameters based on feature set
  • Work with leads to deliver the SOC RTL, Netlist, power collateral, constraints.
  • Work with Systems/SW team in performance analysis and propose IP enhancements or any new IP requirement in the SOC
  • Technical guidance for Corrective and Preventive Action planning and Tracking
  • Provide technical leadership of all aspects of VLSI development including SoC system aspects, SoC architecture, front end design, SoC Integration, Static checks, low power design, DFT, implementation, chip bring-up, debug, and transforming from first sample through release to volume production.
  • Responsible for overall chip schedule and coordinating with multiple teams on specifications, deliverables, handoff, verification and timing closure.
  • Knowledge in Lint, CDC, timing constraints, synthesis, STA, power analysis

Qualifications

Job Qualification

  • Bachelor’s or Master's degree in appropriate engineering discipline with 14 to 20 years of experience in design and delivery of IPs, Subsystems, and SOCs
  • Strong fundamentals in CPU architecture, Host interfaces like (PCIe, SDIO etc.), Bus interconnects specially AXI/ACE/AHB/APB, Low power design.
  • Power management with multiple power domains
  • Proven track record as SOC lead/architect of bringing logic designs into high volume production
  • Strong understanding of the SOC development flow
  • Experience in defining and using advanced front-end design flows based on industry standard EDA tools from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team
  • Should possess strong communication and leadership skills to ensure effective communication with Program Management or Engineering Management and group members

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