Synaptics

Senior ASIC Design Engineer

Job Locations CN-Chengdu
ID
2022-3126
Category
R&D
Type
Employee

Overview

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Responsibilities

  • SOC top level or subsystem architecture definition, SOC integration and RTL coding for block or top level
  • Assist on Verification engineer to complete block/top level simulation and verification (RTL/Gate level)
  • Timing constraint/SDC development
  • Top level and block level synthesis
  • Top level and block level timing analysis and closure
  • Low power design and verification
  • Formal verification (functional equivalence check)
  • Chip and IP level LINT/CDC check
  • Interaction/co-ordination with different cross-functional (digital-design/analog-design/physical-design/verification/validation/software) teams across different world geographies

Qualifications

  • MSEE with 5+ years’ experience or bachelor with 8+ years’ experience in digital design
  • Proficient in Verilog and System Verilog
  • Familiar with SOC architecture and bus protocol including ACE/AXI/AHB
  • Experience in ASIC implementation flow like lint/CDC, Synthesis, Formal and STA
  • Experience of SOC integration, low power design
  • Experience of FPGA design is a plus
  • Experience of DFT/Physical tool and flow will be a plus
  • Basic skills of script and be familiar with TCL, Perl, etc.
  • Excellent communication skills and fluent in English

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