Synaptics

Sr. Digital Engineer

Job Locations IN-Bengaluru
ID
2022-3144
Category
R&D
Type
Employee

Overview

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Responsibilities

The Edge SoC Silicon R&D team is looking for a hands-on, team oriented engineer with front-end SoC/ASIC RTL design/integration/implementation expertise. In this individual contributor role, candidate will have complete ownership of SoC/ASIC RTL designs (subsystem or full chip level) from specification to silicon validation. Candidate should have hands-on knowledge of Architecture/Micro-Architecture design, SoC/ASIC RTL design, Functional Simulation, Synthesis, Formal Verification, CDC Analysis, Static Timing Analysis and DFT at Physical partition or full chip level of SoC/ASIC. Candidate should have strong ability to learn and explore new technologies. Candidate is desired to have expertise in SoC/ASIC CAD tool flow development and ability to demonstrate good analysis and problem-solving skills. Candidate is desired to have an extraordinarily creative and motivated  approach towards complex design problems. Candidate must be highly organized, able to prioritize, and juggle multiple work streams towards tight deadlines.

 

Candidate will be responsible for combination of following executables based on project requirements:

  • Study of Functional Specification/Requirement documents, Standard documents
  • Architecture/Micro-Architecture understanding/development for existing/new designs
  • Verilog/SystemVerilog/VHDL RTL design of [FSM, Complex Data path/Control Path Designs]
  • Clock-Structure design, Reset-Structure designs
  • Power aware RTL coding/design
  • Full Chip level RTL design integration
  • Synthesis/STA Constraint modelling/validation
  • Logic Synthesis (using Design-Compiler or equivalent industry tools)
  • Formal Verification (using Formality, Conformal or equivalent industry tools)
  • CDC (using Spyglass or equivalent industry tools)
  • Static Timing Analysis (using Primetime or Encounter Timing System)
  • Power Analysis (Primepower or equivalent industry tools)
  • FPGA/Pre-Si(SDF-GLS)/PostSi/System validation, debug
  • Interaction/co-ordination with different cross-functional (digital-design/analog-design/physical-design/verification/validation/software) teams across different world geographies

Qualifications

  • At least 6+ years of SoC/ASIC Design with good working understanding/experience/knowledge of following is must:
  • SoC/ASIC RTL design/integration using HDL languages like VerilogHDL, VHDL, SystemVerilog
  • AXI3/AXI4, AHB, APB, UART, SPI, I2C, DDR2/3/4/LPDDR2/3/4, DDR PHY interface (DFI), PCIe Standards/Protocols
  • SoC/ASIC full-chip (integration/fabric) Design/Floorplan experience
  • Clock, Reset Structures/Schemes, control path-oriented designs and asynchronous multiple clock designs.
  • Full Chip I/O Pad ring, Packaging
  • ASIC tool flow environment setup: Spyglass-lint/CDC, Design Compiler(T), Formality, PrimeTime, PrimePower
  • DFT Techniques/Structures
  • Simulator tools: VCS, Questa
  • Waveform viewer tool: Verdi
  • Scripting: Perl, Tcl, Shell, C, C++ languages

 

  • Following skills are must:
  • Hands on RTL integration, synthesis, timing closure experience of minimum 3 tape-out cycles at physical-partition/block/tile or chip level, delivering best Power Performance Area for block/tile with critical high-speed path timing closure
  • Strong Analytical, Problem solving, Debugging skills
  • Excellent Oral/Written Communication and Technical Documentation Skills
  • Knowledge of revision control tools such as SOS, Git, synchronicity etc.

 

  • Following additional skills a plus:
  • Knowledge and exposure to complete Netlist to GDS to silicon release flow is desired
  • Hands on experience with MBIST, Scan insertion, ATPG, BIST, JTAG, physical design tools and flow.
  • Hands on experience with Low power design methodology & techniques like UPF, DVFM, Multi-voltage etc.
  • Knowledge of connectivity Standards/Protocols like Ethernet, Wi-Fi, WLAN, Bluetooth etc.
  • Knowledge of various Audio, Video specification/standards/protocols like I2S, SPDIF, HDMI, DisplayPort, LVDS, MIPI
  • Knowledge of various Video, Audio formats

 

  • BE/BTech/ME/MTech in Electrical/Electronics/VLSI Design/Communications/Image processing/Audio processing/DSP or a related technical discipline

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